1. Field of the Invention
The present invention pertains to integrated circuits made with C-MOS (complementary metal oxide semiconductor) technology, and more especially to a read amplifier for memories.
2. Description of the Prior Art
In integrated circuit memories such as RAMs (random-access memories) or similar memories, the data recorded in the memory cells is generally read by means of differential amplifiers. As shown in FIG. 1, which pertains to a circuit made with C-MOS technology, the differential amplifiers used comprise, in a conventional type of assembly, a current supply source consisting of an N type MOS transistor TN3 supplying current, in parallel, to two groups of series-connected MOS transistors, respectively consisting, firstly, of an N type MOS transistor TN1 and a P type MOS transistor TP1 and, secondly, of an N type MOS transistor TN2 and a P type MOS transistor TP2.
More specifically, the two groups of MOS transistors, namely TN1, TP1 and TN2, TP2, are mounted between the drain of the MOS transistor TN3 and the power supply voltage V.sub.cc. The control gates of the transistors TN1 and TN2 constitute the inputs E1 and E2 of the differential stage. Furthermore, the assembly described with reference to FIG. 1 is a conventional arrangement of a differential stage with five MOS transistors in a current mirror assembly. Thus, the drain of the MOS transistor TP1 is connected with its control gate which is itself, connected to the control gate of the transistor TP2. In this case, a single, zero or positive, non-differential output voltage S is obtained. This output S is obtained at the drain of the transistor TN2.
This differential stage further comprises an balancing circuit CE consisting, in a known way, of a conventional type of transfer gate controlled by a pre-charging signal PR and its inverted signal PR. This circuit can be used, during an balancing stage, achieved before each read operation, to position the output S of the differential stage towards its common-mode value, namely the value of the output voltage when the inputs E1 and E2 are short-circuited. This balancing circuit is essential in read amplifiers to obtain very fast access times.
However, this balancing circuit has a number of disadvantages. For, if the common-mode value corresponds to a logical level "1" and if two logical levels "0" have to be read successively at the output, there will be a signal with two switch-overs at the output S, i.e. at the start of the balancing process, a transition from a logical level "0" to a logical level "1" followed, during reading, by a transition from a logical level "1" to the logical level "0". Now this entails an increase in the consumption of the circuit and creates a risk of noise in the power supplies.